A Two Input One Output Bit Scalable Architecture for Fuzzy Processors
Roberto d'Amore       Karl Heinz Kienitz     Osamu Saotome
             
Several hardware architectures to implement fuzzy processors have been proposed to satisfy real-time requirements, but very few of these are suitable for automatic synthesis. The presents bit scalable architecture presented allows the automatic synthesis of fuzzy processors in different bit wide resolution. The synthesis is made from a VHDL description, and the size of the internal units is defined from a small number of parameters in the highest level entity.

 
                  Nebul_2_2
Processor block diagram

  Nebul_2_3
Processor operations for one sample: fuzzification, inference and defuzzification

Nebul_2_8                        Nebul_2_9
Active rule detection process Defuzzification unit with cti = u

Simulation of the proposed architecture:
Nebul_2_4                                 Nebul_2_5
Fuzzification unit - block diagram Division unit

Control surface for two different conditions of input vz
           
Nebul_2_6                                     Nebul_2_7  

                                 
Results obtained in the synthesis for
different conditions of u and n.		 Control surface generated by the simulation
of a synthesized processor with u = 10

Artigos publicados
D'AMORE, R. . A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors. Ieee Design Test Of Computers, Estados Unidos da América, v. 18, p. 56-64, 2001.

D'AMORE, R. ; KIENITZ, K. H. ; SAOTOME, Osamu . A Bit Scalable Architecture for Fuzzy Processors. In: XIII Symposium on Integrated Circuits and Systems Design, 1999, Natal. Proceedings SBCCI99. Los Alamitos, CA : IEEE Computer Society, 1999. v. 1. p. 8-11.

D'AMORE, R. ; SAOTOME, Osamu ; KIENITZ, K. H. . Automatic synthesis of membership functions generators for fuzzy logic. In: International Conference on Microelectronics and Packaging ICMP 98, 1998, Curitiba. Proceedings XIII SBMICRO, 1998. v. I. p. 95-101.

D'AMORE, R. ; SAOTOME, Osamu ; KIENITZ, K. H. . Architecture of a fuzzy logic processor with detection of active rules and pipeline. In: XIII SBMicro. International Conference on Microelectronics and Packaging ICMP 98, 1998, Curitiba. Proceedings XIII SBMICRO, 1998. v. I. p. 109-115.

D'AMORE, R. ; KIENITZ, K. H. . Controlador nebuloso com detecção de regras ativas. In: 3o Simpósio Brasileiro de Automação Inteligente 1997, 1997, Vitória. 3o SBAI, 1997. v. 1. p. 313-318.