A bit scalable architecture for fuzzy processors with three inputs
and a flexible fuzzification unit
Roberto d'Amore
             
 An architecture of a three input one output  bit scalable fuzzy processor. The synthesis is made from a VHDL description. The data path and functional units dimension are defined by a small number of parameters in the highest level entity. The knowledge base and the membership functions are stored in distinct units in the circuit description for an easy control strategy modification.

Nebul_3_1.gif                                         Nebul_3_2.gif
Fuzzification unit - block diagram Processor block diagram

Nebul_3_4.gif                                         Nebul_3_6.gif
Fuzzification unit - block diagram Division unit

Simulation of the proposed architecture:
a control strategy with  9 input membership functions, 7 output membership functions
 
Nebul_a.gif                                      Nebul_b.gif      

Input membership functions		 Rules set  control
and
Rules association matrix output.

Control surface for two different conditions of input vz
                
Nebul_10Nebul_3_7                         Nebul_10Nebul_3_8
                                        
Control surface for z=32. Control surface z=244.

Artigo publicado
D'AMORE, R. . A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification Unit. In: 13th Symposium on Integrated Circuits and System Design - SBCCI 2000, 2000, Manaus. Proceedings SBCCI 2000. Los Alamitos, CA : IEEE Computer Society, 2000. v. 1. p. 29-34.