Telemety Reception Circuit with Low-Cost FPGA

Tese de Mestrado de Luis Fernando Galdieri

This work describes the design of a telemetry reception circuit that operates whit telemetry frames according standard IRIG 106-96.  This circuit is divided in three parts: clock recover, synchronism and interface. The clock recovery operation is limited to data rates lower than 250kbps. The synchronism circuit operates with 20-bit word synchronism and the interface circuit allows a communication with 8-bit microprocessors.

Telemetry systems are employed to monitor the data of remote equipments and transmit them to a distant station. Aerospace, automobiles and defense industries use these systems, but we can also see them applied in others areas like amusement, patient monitoring and biological studies. The telemetry of a car during a race, for example, once used only by the team for monitoring purposes, is now available to the television spectator in real time.

The cost of telemetry systems is very high due to their wide range of configuration options. If we restrict these options to a particular set of characteristic, it is possible to implement a low-cost system that satisfies some specific applications.

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Telemety reception block diagram

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PCM code representation
PCM frame format 

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Circuit block diagram Clock recovering and synchronization

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Leonardo Spectrum synthesis RTL level Test

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The "Sinc Frame" signal (inferior part) is only activated when
20 bits of PCM signal match with the bits of the synchronism word.
In this example, the sequence "11101101111000100000" was received
and "Sinc Frame" goes high at the center of the figure.
Note that the most significant bit of the PCM data is the last data received

The "New Word" signal is activated for each 10 bits received.
For example, the forth word received  (superior part) is
“0001111011” (less significant bit first).
The time bit is 4us and the “New Word” signal is activated in 40us.


Artigo publicado
GALDIERI, L. F.; D'AMORE, R. Telemetry Reception Circuit Using Low-Cost FPGA. In: IMAPS Brasil 2005 International Technical Symposium on Packaging, Assembling & Exhibition.