Soluções do capítulo 2

Exercício 2.7.1
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 ENTITY std_ya IScapa_1ra
  PORT (a, b, c, d  : IN     BIT;
        s1          : BUFFER BIT;
        s2, s3, s4  : OUT    BIT);                    
END std_ya;

ARCHITECTURE teste OF std_ya IS
BEGIN
  s1 <= a OR NOT b;
  s2 <= a OR (NOT b AND c) OR d;
  s3 <= s1 AND (c OR d);
  s4 <= s1 AND NOT(c OR (a AND d));
END teste;

Exercício 2.7.7
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   ENTITY corret_1 IScapa_1ra
  PORT (a, b, c, d : IN  BIT;
        s          : OUT BIT_VECTOR (5 DOWNTO 0));
END corret_1;

ARCHITECTURE teste OF corret_1 IS
BEGIN
  s(0) <= (a AND  b) OR (c AND d); -- opcao 1
--s(0) <=  a AND  (b OR c) AND d;  -- opcao 2

  s(1) <= (a NOR b) NOR c;         -- opcao 1
--s(1) <=  a NOR (b NOR c);        -- opcao 2

  s(2) <= (a AND  b) OR c;         -- opcao 1
--s(2) <=  a AND  (b OR c);        -- opcao 2

  s(3) <= NOT (a AND b) NAND c;    -- correta
  s(4) <= a XOR  b XOR c;          -- correta 
END teste;