VHDL Descrição e Síntese de Circuitos Digitais

Soluções do capítulo 11

Exercício 11.5.1

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-- versao VDHL-1993 para os operadores sll, srl rol e ror capa_1ra

LIBRARY ieee;
USE ieee.numeric_std.ALL;

ENTITY std1076x IS
PORT (x_s              : IN   SIGNED (3 DOWNTO 0);
        x_u              : IN   UNSIGNED(3 DOWNTO 0);

        s_shift_left     : OUT SIGNED (3 DOWNTO 0);
        u_shift_left     : OUT UNSIGNED(3 DOWNTO 0);
        s_sll            : OUT SIGNED (3 DOWNTO 0);
        u_sll            : OUT UNSIGNED(3 DOWNTO 0);

        s_shift_right    : OUT SIGNED (3 DOWNTO 0);
        u_shift_right    : OUT UNSIGNED(3 DOWNTO 0);
        s_srl            : OUT SIGNED (3 DOWNTO 0);
        u_srl            : OUT UNSIGNED(3 DOWNTO 0);

        s_rotate_left    : OUT SIGNED (3 DOWNTO 0);
        u_rotate_left    : OUT UNSIGNED(3 DOWNTO 0);
        s_rol            : OUT SIGNED (3 DOWNTO 0);
        u_rol            : OUT UNSIGNED(3 DOWNTO 0);

        s_rotate_right   : OUT SIGNED (3 DOWNTO 0);
        u_rotate_right   : OUT UNSIGNED(3 DOWNTO 0);
        s_ror            : OUT SIGNED (3 DOWNTO 0);
        u_ror            : OUT UNSIGNED(3 DOWNTO 0);

        n                : IN   NATURAL RANGE 0 TO 3;
        i                : IN   INTEGER RANGE -3 TO 3);
END std1076x;

ARCHITECTURE teste OF std1076x IS
BEGIN
s_shift_left <= shift_left (x_s, n);
s_shift_right <= shift_right(x_s, n);

s_rotate_left <= rotate_left (x_s, n);
s_rotate_right <= rotate_right(x_s, n);

s_sll <= x_s sll i;       -- ou notacao chamada de funcao: s_sll <= "sll"(x_s, i);
s_srl <= x_s srl i;       -- ou notacao chamada de funcao: s_srl <= "srl"(x_s, i);

s_rol <= "rol"(x_s, i);   -- ou notacao operador: s_rol <= x_s rol i;
s_ror <= "ror"(x_s, i);   -- ou notacao operador: s_ror <= x_s ror i;

u_shift_left <= shift_left (x_u, n);
u_shift_right <= shift_right(x_u, n);

u_rotate_left <= rotate_left (x_u, n);
u_rotate_right <= rotate_right(x_u, n);

u_sll <= "sll"(x_u, i);   -- ou notacao operador
u_srl <= "srl"(x_u, i);   -- ou notacao operador

u_rol <= "rol"(x_u, i);   -- ou notacao operador
u_ror <= "ror"(x_u, i);   -- ou notacao operador
END teste;

Exercício 11.5.6

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LIBRARY ieee; capa_1ra

USE ieee.numeric_bit.ALL;

ENTITY std1076n IS
GENERIC (n : NATURAL RANGE 32 DOWNTO 1 := 4);

PORT (rs               : IN   SIGNED (n-1 DOWNTO 0);
        ss               : IN   SIGNED (n-1 DOWNTO 0);
        opr              : IN   BIT_VECTOR (2 DOWNTO 0);
        ci               : IN   BIT;                     -- carry in
        ov               : OUT BIT;                     -- overflow
        zr               : OUT BIT;                     -- zero
        ts               : OUT SIGNED (n-1 DOWNTO 0));
END std1076n;

ARCHITECTURE teste OF std1076n IS
SIGNAL zero_a : SIGNED(n-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL zero_b : SIGNED(n-2 DOWNTO 0) := (OTHERS => '0');
BEGIN

alu:PROCESS (rs, ss, ci, opr)
    VARIABLE over : BIT_VECTOR(2 DOWNTO 0);
    VARIABLE tis : SIGNED(n-1 DOWNTO 0);
    VARIABLE soma : BOOLEAN;
BEGIN
CASE opr IS
    WHEN "000" => tis := rs + ss;                soma := TRUE;
    WHEN "001" => tis := rs + ss + (zero_b &ci); soma := TRUE;
    WHEN "010" => tis := rs - ss;                soma := FALSE;
    WHEN "011" => tis := rs - ss - (zero_b &ci); soma := FALSE;
    WHEN "100" => tis := rs AND ss;                soma := FALSE;
    WHEN "101" => tis := rs OR ss;                soma := FALSE;
    WHEN "110" => tis := rs XOR ss;                soma := FALSE;
    WHEN "111" => tis := NOT rs;                   soma := FALSE;
END CASE;

over := rs(n-1) &ss(n-1) &tis(n-1);
CASE soma IS
    WHEN TRUE =>
      CASE over IS                       -- 0     0     1,   1     1     0
        WHEN "001" | "110" => ov <= '1'; -- pos + pos = neg, neg + neg = pos
        WHEN OTHERS        => ov <= '0';
      END CASE;
    WHEN FALSE =>
      CASE over IS                       -- 1     0     0,   0     1     1
        WHEN "100" | "011" => ov <= '1'; -- neg - pos = pos, pos - neg = neg
        WHEN OTHERS        => ov <= '0';
      END CASE;
END CASE;

IF tis = zero_a THEN zr <= '1';
ELSE               zr <= '0';
END IF;

ts <= tis;
END PROCESS;

END teste;